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MC68HC908QY4A, MC68HC908QT4A, MC68HC908Qy761A, MC68HC908QT2A, MC68HC908QY1A, MC68HC908QT1A - Data Sheet
Freescale Semiconductor
Inc.
The MC68HC908QY4A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
MC68HC908QY4A, MC68HC908QT4A, MC68HC908Qy761A, MC68HC908QT2A, MC68HC908QY1A, MC68HC908QT1A, M68HC08 Family, CPU08
2010-03-17T14:10:16Z
FrameMaker 7.2
2012-10-04T14:48:19-05:00
2012-05-07T11:48:18-05:00
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2006
MC68HC908QY4A, MC68HC908QT4A, MC68HC908Qy761A, MC68HC908QT2A, MC68HC908QY1A, MC68HC908QT1A, M68HC08 Family, CPU08
2006
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(I7.1.861651) 3706 0 R (I7.1.861664) 3707 0 R (I7.1.862797) 3708 0 R (I7.1.869637) 3709 0 R (I7.1.870246) 3710 0 R
(I8.1.842887) 3711 0 R (I8.1.843437) 3712 0 R (I8.1.843440) 3713 0 R (I8.1.843450) 3714 0 R (I8.1.843563) 3715 0 R
(I8.1.843706) 3716 0 R (I8.1.843727) 3717 0 R (I8.1.843732) 3718 0 R (I8.1.843735) 3719 0 R (I8.1.843745) 3720 0 R
(I8.1.843746) 3721 0 R (I8.1.843748) 3722 0 R (I8.1.843860) 3723 0 R (I8.1.843888) 3724 0 R (I8.1.843889) 3725 0 R
(I8.1.844657) 3726 0 R (I8.1.844665) 3727 0 R]
/Limits [(I7.1.861268) (I8.1.844665)]
>>
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/Names [(I8.1.845412) 3728 0 R (I8.1.845413) 3729 0 R (I8.1.845415) 3730 0 R (I8.1.845554) 3731 0 R (I8.1.848272) 3732 0 R
(I8.1.848498) 3733 0 R (I8.1.848685) 3734 0 R (I8.1.848687) 3735 0 R (I8.1.848688) 3736 0 R (I8.1.848696) 3737 0 R
(I8.1.848700) 3738 0 R (I8.1.848706) 3739 0 R (I8.1.852629) 3740 0 R (I8.1.852630) 3741 0 R (I8.1.852638) 3742 0 R
(I8.1.852666) 3743 0 R (I8.1.853167) 3744 0 R (I8.1.853168) 3745 0 R (I8.1.853169) 3746 0 R (I8.1.853170) 3747 0 R
(I9.1.824779) 3748 0 R (I9.1.825798) 3749 0 R (I9.1.825799) 3750 0 R (I9.1.825801) 3751 0 R (I9.1.825803) 3752 0 R
(I9.1.829986) 3753 0 R (I9.1.834150) 3754 0 R (I9.1.834333) 3755 0 R (I9.1.837379) 3756 0 R (I9.1.837730) 3757 0 R
(I9.1.837731) 3758 0 R (L) [117 0 R /XYZ null null null]
(L1) 3759 0 R]
/Limits [(I8.1.845412) (L1)]
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/Names [(L10) 3760 0 R (L11) 3761 0 R (L12) 3762 0 R (L13) 3763 0 R (L14) 3764 0 R
(L15) 3765 0 R (L16) 3766 0 R (L17) 3767 0 R (L18) 3768 0 R (L19) 3769 0 R
(L2) 3770 0 R (L20) 3771 0 R (L21) 3772 0 R (L22) 3773 0 R (L23) 3774 0 R
(L3) 3775 0 R (L4) 3776 0 R (L5) 3777 0 R (L6) 3778 0 R (L7) 3779 0 R
(L8) 3780 0 R (L9) 3781 0 R (M10.8.newlink.152) 3782 0 R (M10.8.newlink.153) 3783 0 R (M10.8.newlink.154) 3784 0 R
(M10.8.newlink.1541) 3785 0 R (M10.8.newlink.1542) 3786 0 R (M10.8.newlink.1543) 3787 0 R (M10.8.newlink.1544) 3788 0 R (M10.8.newlink.1546) 3789 0 R
(M10.8.newlink.1547) 3790 0 R (M10.8.newlink.155) 3791 0 R (M10.8.newlink.156) 3792 0 R (M10.8.newlink.157) 3793 0 R (M10.8.newlink.158) 3794 0 R
(M10.8.newlink.1581) 3795 0 R (M10.8.newlink.1582) 3796 0 R (M10.8.newlink.159) 3797 0 R (M10.9.46058.figuretitle.Figure.131..COP.Block.Diagram) 3798 0 R (M10.9.68311.figuretitle.Figure.62..COP.Control.Register.COPCTL) 3799 0 R
(M11.9.12928.sectionx.Section.7.Central.Processor.Unit.CPU) 3800 0 R (M11.9.70017.figuretitle.Figure.11..CPU.Registers) 3801 0 R (M11.9.86244.tabletitle.Table.61..Instruction.Set.Summary.Sheet.1.of.7) 3802 0 R (M11.9.97010.tabletitle.Table.62..Opcode.Map) 3803 0 R (M12.8.newlink.106) 3804 0 R
(M12.8.newlink.114) 3805 0 R (M12.8.newlink.145) 3806 0 R (M12.8.newlink.146) 3807 0 R (M12.9.23226.figuretitlewide.Figure.81..Block.Diagram.Highlighting.ADC10.Block.and.Pins) 3808 0 R (M12.9.50963.figuretitle.Figure.141..IRQ.Module.Block.Diagram) 3809 0 R
(M12.9.57568.sectionx.Chapter.8.External.Interrupt.IRQ) 3810 0 R (M12.9.80706.figuretitle.Figure.113..IRQ.Status.and.Control.Register.INTSCR) 3811 0 R (M13.8.newlink.106) 3812 0 R (M13.8.newlink.114) 3813 0 R (M13.8.newlink.142) 3814 0 R
(M13.8.newlink.143) 3815 0 R (M13.8.newlink.144) 3816 0 R (M13.8.newlink.1441) 3817 0 R (M13.8.newlink.1442) 3818 0 R (M13.8.newlink.1443) 3819 0 R
(M13.8.newlink.145) 3820 0 R (M13.8.newlink.146) 3821 0 R (M13.8.newlink.147) 3822 0 R (M13.9.18793.figuretitle.Figure.95..Keyboard.Interrupt.Polarity.Register.KBIPR) 3823 0 R]
/Limits [(L10) (M13.9.18793.figuretitle.Figure.95..Keyboard.Interrupt.Polarity.Register.KBIPR)]
>>
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/Names [(M13.9.23295.figuretitle.Figure.143..Keyboard.Status.and.Control.Register.KBSCR) 3824 0 R (M13.9.25545.sectionx.Chapter.9.Keyboard.Interrupt.Module.KBI) 3825 0 R (M13.9.37312.figuretitlewide.Figure.91..Block.Diagram.Highlighting.KBI.Block.and.Pins) 3826 0 R (M13.9.39267.figuretitlewide.Figure.142..Keyboard.Interrupt.Block.Diagram) 3827 0 R (M13.9.43703.sectionxxx.1482.Keyboard.Interrupt.Enable.Register) 3828 0 R
(M13.9.55841.sectionxxx.1481.Keyboard.Status.and.Control.Register) 3829 0 R (M13.9.73706.figuretitle.Figure.144..Keyboard.Interrupt.Enable.Register.KBIER) 3830 0 R (M14.8.newlink.162) 3831 0 R (M14.8.newlink.163) 3832 0 R (M14.8.newlink.164) 3833 0 R
(M14.8.newlink.1641) 3834 0 R (M14.8.newlink.1642) 3835 0 R (M14.8.newlink.1644) 3836 0 R (M14.8.newlink.165) 3837 0 R (M14.8.newlink.166) 3838 0 R
(M14.8.newlink.167) 3839 0 R (M14.8.newlink.1671) 3840 0 R (M14.8.newlink.1672) 3841 0 R (M14.9.11780.figuretitle.Figure.161..LVI.Module.Block.Diagram) 3842 0 R (M14.9.23822.sectionxx.84.Functional.Description) 3843 0 R
(M14.9.28544.figuretitle.Figure.82..LVI.Status.Register.LVISR) 3844 0 R (M14.9.92717.tabletitle.Table.182..LVIOUT.Bit.Indication) 3845 0 R (M15.8.newlink.106) 3846 0 R (M15.8.newlink.114) 3847 0 R (M15.8.newlink.145) 3848 0 R
(M15.8.newlink.146) 3849 0 R (M15.8.newlink.82) 3850 0 R (M15.8.newlink.83) 3851 0 R (M15.8.newlink.832) 3852 0 R (M15.8.newlink.84) 3853 0 R
(M15.8.newlink.85) 3854 0 R (M15.8.newlink.86) 3855 0 R (M15.8.newlink.873) 3856 0 R (M15.8.newlink.874) 3857 0 R (M15.8.newlink.875) 3858 0 R
(M15.8.newlink.876) 3859 0 R (M15.8.newlink.877) 3860 0 R (M15.8.newlink.878) 3861 0 R (M15.9.16208.sectionxxxx.11312.Internal.to.External.Clock.Switching) 3862 0 R (M15.9.18921.sectionxxx.1182.Oscillator.Trim.Register.OSCTRIM) 3863 0 R
(M15.9.23357.figuretitlewide.Figure.101..Block.Diagram.Highlighting.OSC.Block.and.Pins) 3864 0 R (M15.9.43665.figuretitle.Figure.103..RC.Oscillator.External.Connections) 3865 0 R (M15.9.64519.figuretitle.Figure.83..Oscillator.Status.Register.OSCSTAT) 3866 0 R (M15.9.73637.figuretitle.Figure.81..XTAL.Oscillator.External.Connections) 3867 0 R (M15.9.75855.sectionx.Chapter.11.Oscillator.OSC.Module) 3868 0 R
(M15.9.77602.figuretitle.Figure.84..Oscillator.Trim.Register.OSCTRIM) 3869 0 R (M15.9.83267.sectionxxx.1171.Oscillator.Status.Register) 3870 0 R (M15.9.97190.sectionxxxx.8411.Internal.Oscillator.Trimming) 3871 0 R (M16.8.newlink.122) 3872 0 R (M16.8.newlink.123) 3873 0 R
(M16.8.newlink.1231.) 3874 0 R (M16.8.newlink.1232) 3875 0 R (M16.8.newlink.1233) 3876 0 R (M16.8.newlink.124) 3877 0 R (M16.8.newlink.1241) 3878 0 R
(M16.8.newlink.1242) 3879 0 R (M16.8.newlink.1243) 3880 0 R (M16.8.newlink.141) 3881 0 R (M16.8.newlink.1411) 3882 0 R (M16.8.newlink.1412) 3883 0 R
(M16.8.newlink.t141) 3884 0 R (M16.9.15906.tabletitle.Table.103..Port.B.Pin.Functions) 3885 0 R (M16.9.18258.tabletitle.Table.102..Port.A.Pin.Functions) 3886 0 R (M16.9.19426.tablefootnote.1.X..dont.care) 3887 0 R]
/Limits [(M13.9.23295.figuretitle.Figure.143..Keyboard.Status.and.Control.Register.KBSCR) (M16.9.19426.tablefootnote.1.X..dont.care)]
>>
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/Names [(M16.9.22036.sectionxxx.1342.Port.A.Input.Pullup.Enable.Register.PTAPUE) 3888 0 R (M16.9.24458.figuretitle.Figure.17..Port.B.IO.Circuit) 3889 0 R (M16.9.27061.figuretitle.Figure.123..Data.Direction.Register.A.DDRA) 3890 0 R (M16.9.28033.tablefootnote.3.footnote3) 3891 0 R (M16.9.35776.figuretitle.Figure.125..Port.A.Input.Pullup.Enable.Regiser.PTAPUE) 3892 0 R
(M16.9.37233.tablefootnote.3.Writing.affects.data.register.but.does.not.affect.the.input) 3893 0 R (M16.9.40512.figuretitle.Figure.133..Port.A.IO.Circuit) 3894 0 R (M16.9.43097.sectionxxx.1231.Port.A.Data.Register) 3895 0 R (M16.9.48619.figuretitle.Figure.122..Port.A.Data.Register.PTA) 3896 0 R (M16.9.50213.figuretitle.Figure.127..Data.Direction.Register.B.DDRB) 3897 0 R
(M16.9.69884.figuretitle.Figure.126..Port.B.Data.Register.PTB) 3898 0 R (M16.9.78292.sectionxx.121.Introduction) 3899 0 R (M16.9.82413.sectionx.Chapter.12.InputOutput.Ports.PORTS) 3900 0 R (M16.9.87503.figuretitle.Figure.129) 3901 0 R (M16.9.94884.sectionxxx.1242.Data.Direction.Register.B.DDRB) 3902 0 R
(M17.8.newlink.72) 3903 0 R (M17.8.newlink.721) 3904 0 R (M17.8.newlink.73) 3905 0 R (M17.8.newlink.731) 3906 0 R (M17.8.newlink.732) 3907 0 R
(M17.8.newlink.733) 3908 0 R (M17.8.newlink.74) 3909 0 R (M17.8.newlink.741) 3910 0 R (M17.8.newlink.742) 3911 0 R (M17.8.newlink.7421) 3912 0 R
(M17.8.newlink.7422) 3913 0 R (M17.8.newlink.7423) 3914 0 R (M17.8.newlink.7424) 3915 0 R (M17.8.newlink.7425) 3916 0 R (M17.8.newlink.75) 3917 0 R
(M17.8.newlink.751) 3918 0 R (M17.8.newlink.752) 3919 0 R (M17.8.newlink.753) 3920 0 R (M17.8.newlink.76) 3921 0 R (M17.8.newlink.761) 3922 0 R
(M17.8.newlink.7611) 3923 0 R (M17.8.newlink.7612) 3924 0 R (M17.8.newlink.762) 3925 0 R (M17.8.newlink.7621) 3926 0 R (M17.8.newlink.7622) 3927 0 R
(M17.8.newlink.7623) 3928 0 R (M17.8.newlink.763) 3929 0 R (M17.8.newlink.764) 3930 0 R (M17.8.newlink.765) 3931 0 R (M17.8.newlink.77) 3932 0 R
(M17.8.newlink.771) 3933 0 R (M17.8.newlink.772) 3934 0 R (M17.8.newlink.78) 3935 0 R (M17.8.newlink.782) 3936 0 R (M17.8.newlink.783) 3937 0 R
(M17.9.10593.sectionxxx.782.Reset.Status.Register.RSR) 3938 0 R (M17.9.14412.figuretitlewide.Figure.74..Internal.Reset.Timing) 3939 0 R (M17.9.24049.figuretitlewide.Figure.11..SIM.Block.Diagram) 3940 0 R (M17.9.27542.sectionxxx.783.Break.Flag.Control.Register.BFCR) 3941 0 R (M17.9.28831.figuretitlewide.Figure.75..Sources.of.Internal.Reset) 3942 0 R
(M17.9.30327.figuretitle.Figure.721..SIM.Reset.Status.Register.SRSR) 3943 0 R (M17.9.40184.sectionxx.75.SIM.Counter) 3944 0 R (M17.9.51423.figuretitlewide.Figure.72..CGM.Clock.Signals) 3945 0 R (M17.9.53083.figuretitle.Figure.714..Interrupt.Status.Register.3.INT3) 3946 0 R (M17.9.55486.figuretitlewide.Figure.712..Wait.Recovery.from.Interrupt.or.Break) 3947 0 R
(M17.9.56260.figuretitle.Figure.714..Stop.Mode.Entry.Timing) 3948 0 R (M17.9.57492.figuretitlewide.Figure.79..Interrupt.Recovery) 3949 0 R (M17.9.57737.sectionxxx.742.Active.Resets.from.Internal.Sources) 3950 0 R (M17.9.61185.figuretitle.Figure.713..Interrupt.Status.Register.2.INT2) 3951 0 R]
/Limits [(M16.9.22036.sectionxxx.1342.Port.A.Input.Pullup.Enable.Register.PTAPUE) (M17.9.61185.figuretitle.Figure.713..Interrupt.Status.Register.2.INT2)]
>>
endobj
107 0 obj
<<
/Names [(M17.9.62935.sectionxx.77.LowPower.Modes) 3952 0 R (M17.9.62981.figuretitlewide.Figure.77..Interrupt.Entry) 3953 0 R (M17.9.63168.figuretitle.Figure.712..Interrupt.Status.Register.1.INT1) 3954 0 R (M17.9.66788.figuretitlewide.Figure.77.Interrupt.Processing) 3955 0 R (M17.9.67581.figuretitlewide.Figure.73..External.Reset.Timing) 3956 0 R
(M17.9.67824.sectionxxx.152.Stop.Mode) 3957 0 R (M17.9.67986.sectionx.Chapter.14.System.Integration.Module.SIM) 3958 0 R (M17.9.75697.sectionxx.86.Exception.Control) 3959 0 R (M17.9.77539.figuretitlewide.Figure.77..POR.Recovery) 3960 0 R (M17.9.82612.figuretitlewide.Figure.713..Wait.Recovery.from.Internal.Reset) 3961 0 R
(M17.9.84762.tabletitle.Table.73..PIN.Bit.Set.Timing) 3962 0 R (M17.9.85338.sectionxx.15.SIM.Control.Registers) 3963 0 R (M17.9.91960.figuretitle.Figure.722..Break.Flag.Control.Register.BFCR) 3964 0 R (M17.9.92185.figuretitlewide.Figure.710..Interrupt.Recognition.Example) 3965 0 R (M17.9.96984.tabletitle.Table.73..Interrupt.Sources) 3966 0 R
(M17.9.97984.figuretitlewide.Figure.711..Wait.Mode.Entry.Timing) 3967 0 R (M17.9.99011.figuretitlewide.Figure.719..Stop.Mode.Recovery.from.Interrupt.or.Break) 3968 0 R (M18.8.newlink.102) 3969 0 R (M18.8.newlink.103) 3970 0 R (M18.8.newlink.105) 3971 0 R
(M18.8.newlink.1052) 3972 0 R (M18.8.newlink.1053) 3973 0 R (M18.8.newlink.10531) 3974 0 R (M18.8.newlink.10532) 3975 0 R (M18.8.newlink.1054) 3976 0 R
(M18.8.newlink.10541) 3977 0 R (M18.8.newlink.10542) 3978 0 R (M18.8.newlink.10543) 3979 0 R (M18.8.newlink.106) 3980 0 R (M18.8.newlink.107) 3981 0 R
(M18.8.newlink.108) 3982 0 R (M18.8.newlink.114) 3983 0 R (M18.8.newlink.1142) 3984 0 R (M18.9.10786.tabletitle.Table.112) 3985 0 R (M18.9.10990.figuretitle.Figure.109..TIM.Channel.Registers.TCH0HLTCH1HL) 3986 0 R
(M18.9.11383.figuretitlewide.Figure.141..Block.Diagram.Highlighting.TIM.Block.and.Pins) 3987 0 R (M18.9.11981.figuretitle.Figure145..TIM.Counter.High.Register.TCNTH) 3988 0 R (M18.9.19781.figuretitle.Figure.107..TIM.Channel.Status.and.Control.Registers.TSC0TSC1) 3989 0 R (M18.9.24304.tabletitle.Table.12..Mode.Edge.and.Level.Selection) 3990 0 R (M18.9.25763.sectionxxx.1481.TIM1.Status.and.Control.Register) 3991 0 R
(M18.9.26090.sectionx.Chapter.14.Timer.Interface.Module.TIM) 3992 0 R (M18.9.26469.figuretitle.Figure.104..TIM.Status.and.Control.Register.TSC) 3993 0 R (M18.9.30151.sectionxxx.1233.Output.Compare) 3994 0 R (M18.9.52674.figuretitle.Figure.105..TIM.Counter.Registers.TCNTHTCNTL) 3995 0 R (M18.9.53514.figuretitle.Figure.106..TIM.Counter.Modulo.Registers.TMODHTMODL) 3996 0 R
(M18.9.60403.figuretitle.Figure.11..TIM.Block.Diagram) 3997 0 R (M18.9.65500.figuretitleindented.Figure.12..PWM.Period.and.Pulse.Width) 3998 0 R (M18.9.65774.figuretitle.Figure147..TIM.Counter.Modulo.High.Register.TMODH) 3999 0 R (M18.9.68893.figuretitle.Figure.18..CHxMAX.Latency) 4000 0 R (M18.9.69348.sectionxxx.134.Pulse.Width.Modulation.PWM) 4001 0 R
(M18.9.74427.figuretitle.Figure1412..TIM.Channel.x.Register.High.TCHxH) 4002 0 R (M18.9.96174.figuretitle.Figure149..TIM.Channel.0.Status.and.Control.Register.TSC0) 4003 0 R (M19.8.newlink.172) 4004 0 R (M19.8.newlink.174) 4005 0 R (M19.8.newlink.1741) 4006 0 R
(M19.8.newlink.1743) 4007 0 R (M19.8.newlink.1744) 4008 0 R (M19.8.newlink.1751) 4009 0 R (M19.8.newlink.1752) 4010 0 R (M19.8.newlink.1753) 4011 0 R
(M19.8.newlink.1754) 4012 0 R (M19.8.newlink.1755) 4013 0 R (M19.8.newlink.176) 4014 0 R (M19.8.newlink.94) 4015 0 R]
/Limits [(M17.9.62935.sectionxx.77.LowPower.Modes) (M19.8.newlink.94)]
>>
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/Names [(M19.8.newlink.942) 4016 0 R (M19.8.newlink.943) 4017 0 R (M19.8.newlink.944) 4018 0 R (M19.8.newlink.945) 4019 0 R (M19.8.newlink.95) 4020 0 R
(M19.9.12115.tabletitle.Table.152..Mode.Differences) 4021 0 R (M19.9.12337.figuretitlewide.Figure.93..Monitor.Mode.Circuit.External.Clock.with.High.Voltage) 4022 0 R (M19.9.15390.tabletitle.Table.199..RUN.Run.User.Program.Command) 4023 0 R (M19.9.17140.sectionxx.172.Break.Module.BRK) 4024 0 R (M19.9.17672.figuretitle.Figure.181..Break.Module.Block.Diagram) 4025 0 R
(M19.9.18129.figuretitle.Figure.158..Monitor.Mode.Entry.Timing) 4026 0 R (M19.9.22604.sectionxxx.1541.Break.Status.and.Control.Register.BRKSCR) 4027 0 R (M19.9.23062.figuretitle.Figure.175..Break.Address.Register.Low.BRKL) 4028 0 R (M19.9.24861.figuretitle.Figure.177..Break.Flag.Control.Register.BFCR) 4029 0 R (M19.9.25358.sectionxx.153.Monitor.Module.MON) 4030 0 R
(M19.9.27542.sectionxxx.783.Break.Flag.Control.Register.BFCR) 4031 0 R (M19.9.29468.sectionxx.155.Security) 4032 0 R (M19.9.30347.figuretitle.Figure.156..Break.Auxiliary.Register.BRKAR) 4033 0 R (M19.9.31873.tabletitle.Table.194..READ.Read.Memory.Command) 4034 0 R (M19.9.40744.tabletitle.Table.151..Monitor.Mode.Signal.Requirements.and.Options) 4035 0 R
(M19.9.51868.figuretitle.Figure.176..Break.Status.Register.BSR) 4036 0 R (M19.9.52768.figuretitlewide.Figure.159..Simplified.Monitor.Mode.Entry.Flowchart) 4037 0 R (M19.9.56181.figuretitle.Figure.13..Break.Transaction) 4038 0 R (M19.9.62980.figuretitle.Figure.174..Break.Address.Register.High.BRKH) 4039 0 R (M19.9.63504.figuretitlewide.Figure.91..Monitor.Mode.Circuit.External.Clock.No.High.Voltage) 4040 0 R
(M19.9.65085.figuretitle.Figure.173..Break.Status.and.Control.Register.BRKSCR) 4041 0 R (M19.9.84103.sectionx.Chapter.17.Development.Support) 4042 0 R (M19.9.93821.figuretitle.Figure.12..Monitor.Data.Format) 4043 0 R (M19.9.99743.figuretitlewide.Figure.92..Monitor.Mode.Circuit.Internal.Clock.No.High.Voltage) 4044 0 R (M20.8.newlink.1810) 4045 0 R
(M20.8.newlink.1814) 4046 0 R (M20.8.newlink.182) 4047 0 R (M20.8.newlink.183) 4048 0 R (M20.8.newlink.184) 4049 0 R (M20.8.newlink.185) 4050 0 R
(M20.8.newlink.186) 4051 0 R (M20.8.newlink.189) 4052 0 R (M20.9.11782.tablefootnote.3.Values.are.based.on.characterization.results.not.tested.in.production) 4053 0 R (M20.9.28389.sectionxx.1615.Timer.Interface.Module.Characteristics) 4054 0 R (M20.9.28701.tablefootnote.1.Bus.frequency.fOP.is.oscillator.frequency.divided.by.4) 4055 0 R
(M20.9.32300.sectionxx.1718.ADC10LV.Characteristics) 4056 0 R (M20.9.34425.figuretitlewide.Figure.191..RC.vs.Frequency.Typ.5V.25C) 4057 0 R (M20.9.37274.sectionxx.199.3V.DC.Electrical.Characteristics) 4058 0 R (M20.9.37700.sectionxx.162.Absolute.Maximum.Ratings) 4059 0 R (M20.9.40923.figuretitlewide.Figure.192..RC.vs.Frequency.Typ.3V.25C) 4060 0 R
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